EPM5192AJI84-20 vs EPM5192AJC84-15 Vergleich
Detaillierter Direktvergleich von EPM5192AJI84-20 von Altera und EPM5192AJC84-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM5192AJC84-15 - MAX 5000 CPLD, 192 Macrocells, 84-pin PLCC | Altera
EPM5192AJC84-15 ObsoleteSpezifikationsvergleich
| Parameter | EPM5192AJI84-20 | EPM5192AJC84-15 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $10,95 | $18,95 |
| Device Family | MAX 5000 (EPM5192) | — |
| Logic Cells / Macrocells | 192 macrocells | — |
| Device Type | UV-Erasable / OTP Complex PLD | EPLD (Erasable Programmable Logic Device) |
| Propagation Delay (tPD) | 33 ns | — |
| Maximum Frequency (fCNT) | 66.7 MHz | — |
| Supply Voltage (VCC) | 5 V nominal (4.5 V to 5.5 V) | 5 V (single supply) |
| Process Technology | CMOS | CMOS EPROM |
| Operating Temperature Grade | Industrial | — |
| Package Code | WQCCJ (JEDEC) | — |
| Package Type | 84-pin J-bend Ceramic Chip Carrier (PLCC-84, JI) | — |
| Montageart | Surface Mount | Surface Mount |
| Terminal Form | J-Bend | — |
| Number of Terminals | 84 | — |
| Programmability | UV-erasable window + OTP | — |
| Pin-Anzahl | 84 | — |
| Lebenszyklusstatus | Obsolete (legacy Altera MAX 5000) | — |
| RoHS-Status | [DATA_NEEDED: RoHS status of EPM5192AJI84-20] | Non-compliant (contains Pb, ceramic windowed package) |
| Family | — | MAX 5000 |
| Macrocells | — | 192 |
| Propagation Delay (tpd) | — | 15 ns |
| Maximum Clock Frequency (fMAX) | — | 83.3 MHz |
| Technology | — | CMOS, UV-erasable EPROM |
| Gehäuse | — | 84-pin PLCC (J84C) windowed ceramic |
| Betriebstemperatur | — | [DATA_NEEDED: commercial/industrial/military grade] |
| Programming Method | — | UV-erase + EPROM programming (windowed package) |
| Logic Blocks | — | 16 Logic Array Blocks (LABs) |
| I/O Pins | — | [DATA_NEEDED: user I/O count] |