EPM5192AJI84-20 vs EPM5192AJC84-15 对比

详细并排对比 EPM5192AJI84-20 出自 Altera 和 EPM5192AJC84-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5192AJI84-20 EPM5192AJC84-15
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $10.95 $18.95
Device Family MAX 5000 (EPM5192) —
Logic Cells / Macrocells 192 macrocells —
Device Type UV-Erasable / OTP Complex PLD EPLD (Erasable Programmable Logic Device)
Propagation Delay (tPD) 33 ns —
Maximum Frequency (fCNT) 66.7 MHz —
Supply Voltage (VCC) 5 V nominal (4.5 V to 5.5 V) 5 V (single supply)
Process Technology CMOS CMOS EPROM
Operating Temperature Grade Industrial —
Package Code WQCCJ (JEDEC) —
Package Type 84-pin J-bend Ceramic Chip Carrier (PLCC-84, JI) —
安装类型 Surface Mount Surface Mount
Terminal Form J-Bend —
Number of Terminals 84 —
Programmability UV-erasable window + OTP —
引脚数量 84 —
生命周期状态 Obsolete (legacy Altera MAX 5000) —
RoHS 状态 [DATA_NEEDED: RoHS status of EPM5192AJI84-20] Non-compliant (contains Pb, ceramic windowed package)
Family — MAX 5000
Macrocells — 192
Propagation Delay (tpd) — 15 ns
Maximum Clock Frequency (fMAX) — 83.3 MHz
Technology — CMOS, UV-erasable EPROM
封装 — 84-pin PLCC (J84C) windowed ceramic
工作温度 — [DATA_NEEDED: commercial/industrial/military grade]
Programming Method — UV-erase + EPROM programming (windowed package)
Logic Blocks — 16 Logic Array Blocks (LABs)
I/O Pins — [DATA_NEEDED: user I/O count]

数据手册与资源

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