EPM5192AQI100-20 vs EPM5192AQM100-20 Vergleich
Detaillierter Direktvergleich von EPM5192AQI100-20 von Altera und EPM5192AQM100-20 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM5192AQI100-20 - MAX 5000 192-Macrocell EPLD, 20ns, PQFP-100 | Altera
EPM5192AQI100-20 ObsoleteIntel
EPM5192AQM100-20 - MAX 5000 CPLD 64 I/O 33ns PQFP-100 | Intel / Altera
EPM5192AQM100-20 ObsoleteSpezifikationsvergleich
| Parameter | EPM5192AQI100-20 | EPM5192AQM100-20 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $18,90 | $8,20 |
| Family | MAX 5000 EPLD | — |
| Device Series | EPM5192 | — |
| Technology | CMOS, UV-erasable EPROM | — |
| Propagation Delay | 20 ns (speed grade -20) | — |
| Logic Array Blocks (LABs) | 12 | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Macrocell Count | 192 | — |
| Dedicated Inputs | 7 | 7 |
| I/O Pins | 64 bidirectional | — |
| Gehäuse | 100-pin PQFP (R-PQFP-G100) | 100-pin PQFP (JESD-30 code R-PQFP-G100) |
| JEDEC Package Outline | R-PQFP-G100 | — |
| Betriebstemperatur | Industrial grade ("I" suffix) | — |
| Montageart | Surface Mount (PQFP) | Surface Mount |
| Architecture | Classic EPLD, deterministic timing | — |
| Design Tool | Altera MAX+PLUS II (legacy) | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: verified from manufacturer product page] |
| Versorgungsspannung | [DATA_NEEDED: VCC range] | [DATA_NEEDED: VCC range from datasheet] |
| Device Family | — | MAX 5000 (EPLD / classic CPLD) |
| Logic Elements | — | 192 macrocells across 12 Logic Array Blocks (LABs) |
| Number of LABs | — | 12 |
| User I/O Lines | — | 64 |
| Pin-to-Pin Propagation Delay (tPD) | — | 33 ns |
| Maximum Clock Frequency (fMAX) | — | 66.7 MHz |
| Process Technology | — | CMOS EPROM-based |
| Configuration Memory | — | On-chip EPROM (non-volatile, one-time programmable in this package) |
| Boundary-Scan Test | — | JTAG / IEEE 1149.1 compatible |
| External Clock Input | — | Yes (global clock pin) |
| Operating Temperature Grade | — | [DATA_NEEDED: explicit temperature grade from datasheet] |