EPM5192GI vs EPM5192GI84 Vergleich

Detaillierter Direktvergleich von EPM5192GI von Altera und EPM5192GI84 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5192GI EPM5192GI84
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $18,95 $19,80
Family MAX 5000 MAX 5000
Device Type CPLD (Complex Programmable Logic Device) UV-Erasable / OTP Complex PLD (CPLD)
Technology CMOS EPROM (UV-erasable / OTP) —
Macrocells 192 192
Logic Array Blocks (LABs) 16 (12 macrocells per LAB) —
User I/O Pins 64 —
Dedicated Inputs 7 —
Total Inputs 72 —
Propagation Delay (tPD) 55 ns —
Maximum Internal Frequency (fCNT) 33.3 MHz —
Supply Voltage (VCC) 4.5 V to 5.5 V (nominal 5 V) —
Betriebstemperatur -40 C to +85 C (Industrial) —
Package Type 84-pin PGA (Pin Grid Array), ceramic with quartz window —
Programmable UV-erasable (windowed) and OTP variants —
Montageart Through-hole (PGA) Through-Hole (PGA socket or PCB pin/peg)
RoHS-Status [DATA_NEEDED: not confirmed in verified web data] [DATA_NEEDED: most legacy PGA parts are non-RoHS]
Logic Array Blocks — [DATA_NEEDED: number of LABs]
Gehäuse — 84-pin PGA (WPGA, square, through-hole, pin/peg terminals)
Package Code — WPGA
Operating Voltage (VCC) — 5 V (typical)
I/O Logic Compatibility — TTL
Temperature Grade — Industrial
Programmable Flip-Flop Modes — D, T, JK, SR
Programmability — UV-erasable (windowed) / OTP
Programming File Format — JEDEC map via MAX+PLUS II / A+PLUS
Propagation Delay — [DATA_NEEDED: tPD in ns]
Max User I/O Pins — [DATA_NEEDED: usable I/O count for this package]
Betriebstemperaturbereich — -40 C to +85 C (industrial)
Lead-Free — [DATA_NEEDED: legacy part, likely contains lead]
Number of Terminals — 84
Terminal Form — PIN/PEG
Package Shape — SQUARE

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