EPM5192GI vs EPM5192GI84 비교

다음의 상세 나란히 비교: EPM5192GI 제조: Altera 및 EPM5192GI84 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EPM5192GI EPM5192GI84
브랜드 Altera Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete Obsolete
재고 상태 In Stock In Stock
단가 (USD) $18.95 $19.80
Family MAX 5000 MAX 5000
Device Type CPLD (Complex Programmable Logic Device) UV-Erasable / OTP Complex PLD (CPLD)
Technology CMOS EPROM (UV-erasable / OTP) —
Macrocells 192 192
Logic Array Blocks (LABs) 16 (12 macrocells per LAB) —
User I/O Pins 64 —
Dedicated Inputs 7 —
Total Inputs 72 —
Propagation Delay (tPD) 55 ns —
Maximum Internal Frequency (fCNT) 33.3 MHz —
Supply Voltage (VCC) 4.5 V to 5.5 V (nominal 5 V) —
동작 온도 -40 C to +85 C (Industrial) —
Package Type 84-pin PGA (Pin Grid Array), ceramic with quartz window —
Programmable UV-erasable (windowed) and OTP variants —
실장 유형 Through-hole (PGA) Through-Hole (PGA socket or PCB pin/peg)
RoHS 상태 [DATA_NEEDED: not confirmed in verified web data] [DATA_NEEDED: most legacy PGA parts are non-RoHS]
Logic Array Blocks — [DATA_NEEDED: number of LABs]
패키지 — 84-pin PGA (WPGA, square, through-hole, pin/peg terminals)
Package Code — WPGA
Operating Voltage (VCC) — 5 V (typical)
I/O Logic Compatibility — TTL
Temperature Grade — Industrial
Programmable Flip-Flop Modes — D, T, JK, SR
Programmability — UV-erasable (windowed) / OTP
Programming File Format — JEDEC map via MAX+PLUS II / A+PLUS
Propagation Delay — [DATA_NEEDED: tPD in ns]
Max User I/O Pins — [DATA_NEEDED: usable I/O count for this package]
동작 온도 범위 — -40 C to +85 C (industrial)
Lead-Free — [DATA_NEEDED: legacy part, likely contains lead]
Number of Terminals — 84
Terminal Form — PIN/PEG
Package Shape — SQUARE

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