EPM5192GM883B-2 vs EPM5192GM Vergleich
Detaillierter Direktvergleich von EPM5192GM883B-2 von Altera und EPM5192GM von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192GM883B-2 | EPM5192GM |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $142,00 | $58,00 |
| Family | MAX 5000 | — |
| Device Type | CPLD (Complex Programmable Logic Device), UV-erasable | UV Erasable Programmable Logic Device (PLD) |
| Macrocells | 192 | — |
| Propagation Delay (tPD) | 45 ns (-2 speed grade) | — |
| Maximum Internal Clock Frequency | 33.3 MHz | — |
| Supply Voltage (VCC, nominal) | 5 V | — |
| Technology | 5 V CMOS | CMOS |
| Dedicated Inputs | 7 | — |
| User I/O Pins | 64 | — |
| Gehäuse | 84-pin Ceramic Pin Grid Array (CPGA), code S-CPGA-P84 | CPGA-84 (Ceramic Pin Grid Array, 84 pins, windowed) |
| Package Outline | 28.45 mm square (approx.) | — |
| Military Screening | MIL-STD-883 (per '883' suffix) | — |
| Montageart | Through-hole PGA socket | Through-Hole (PGA) |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: commercial/industrial/military grade] |
| RoHS-Status | non_compliant (ceramic CPGA with MIL-STD-883 screening) | Non-compliant (contains lead in ceramic PGA) |
| JEDEC Package Code | S-CPGA-P84 | — |
| Product Family | — | MAX 5000 |
| Number of Macrocells | — | 192 |
| Usable Gates | — | 3,750 |
| Pin-to-Pin Delay (tPD) | — | 15 ns (fastest speed grade); 55 ns (this part) |
| Counter Frequency (fCNT) | — | up to 76.9 MHz |
| Propagation Delay (tPD, this part) | — | 55 ns |
| Erasure Method | — | UV (windowed ceramic package) |
| Versorgungsspannung | — | [DATA_NEEDED: typical VCC range] |
| Maximum User I/O | — | [DATA_NEEDED: exact I/O count for CPGA-84] |
| Process Node | — | [DATA_NEEDED: CMOS process geometry] |
| Programming Interface | — | JTAG-compatible (per MAX 5000 family) |