EPM5192JC-1 vs EPM5192JC-2 Vergleich
Detaillierter Direktvergleich von EPM5192JC-1 von Altera und EPM5192JC-2 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192JC-1 | EPM5192JC-2 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $22,40 | $22,50 |
| Family | MAX 5000 | — |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Technology | CMOS, UV-Erasable / OTP | — |
| Macrocells | 192 | 192 |
| Usable Gates | 3750 | — |
| Propagation Delay (tPD) | 40 ns (speed grade -1) | 45 ns |
| Maximum Internal Frequency (fMAX) | 62.5 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| User I/O Pins | 84 | 64 |
| Package Type | 84-pin Ceramic Quad Flat Pack (CQFP), windowed | — |
| JEDEC Package Code | S-CQCC-J84 | — |
| Betriebstemperatur | 0 C to +70 C (commercial) | — |
| Configuration Memory | UV-EPROM (erasable under UV lamp) | — |
| Programming Interface | Altera MAX programming interface (parallel, pre-JTAG for this family) | — |
| Process | CMOS EPROM | — |
| I/O Standard | TTL/CMOS 5 V compatible | — |
| Device Family | — | MAX 5000 |
| Product Type | — | UV-erasable Programmable Logic Device (PLD) |
| Logic Array Blocks (LABs) | — | 12 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Dedicated Inputs | — | 7 |
| External Clock Inputs | — | 1 |
| Maximale Taktfrequenz | — | 40 MHz |
| Process Technology | — | CMOS |
| Gehäuse | — | 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed) |
| Montageart | — | Surface Mount |
| Number of Terminals | — | 84 |
| Programming Method | — | UV-erase / EPROM |
| Betriebstemperaturbereich | — | [DATA_NEEDED: operating temperature range] |
| RoHS-Status | — | [DATA_NEEDED: RoHS compliance] |