EPM5192JC-1N vs EPM5192JC1 Vergleich

Detaillierter Direktvergleich von EPM5192JC-1N von Altera und EPM5192JC1 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5192JC-1N EPM5192JC1
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $19,85 $48,30
Family MAX 5000 MAX 5000 (MAX 5xxx CPLD)
Device Type CPLD - Complex Programmable Logic Device —
Macrocells 192 —
Logic Array Blocks (LABs) 12 —
Usable Gates 3750 3750
User I/O Pins 64 —
Dedicated Inputs 7 —
External Clock Inputs (GCLK) 1 —
Propagation Delay (tPD) 40 ns —
Maximum Clock Frequency (fMAX) 62.5 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V 5 V (nominal)
Technology CMOS EPROM (UV-erasable) —
Gehäuse 84-pin Ceramic Quad Flat Pack (CQFP) [DATA_NEEDED: exact package from datasheet]
JEDEC Package Code S-CQCC-J84 —
Betriebstemperatur [DATA_NEEDED: industrial/commercial temperature range] [DATA_NEEDED: operating temp range]
Programming Interface JTAG / Altera ByteBlaster JTAG-compatible (Altera MAX 5xxx)
Manufacturer — Intel (formerly Altera Corporation)
Macro Cells — 192
Maximum Operating Frequency — 62.5 MHz
Process Technology — 0.5 µm CMOS, UV-erasable EPROM
Propagation Delay (typ) — [DATA_NEEDED: propagation delay in ns]
I/O Pins — [DATA_NEEDED: I/O pin count]
Montageart — [DATA_NEEDED: surface mount or through-hole]
Logic Blocks (LABs) — 24 (8 macrocells per LAB)
RoHS-Status — unknown
AEC-Q100 — not_applicable
Lifecycle — Obsolete - last-time-buy stock only at franchised distributors

Datenblätter & Ressourcen

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