EPM5192JC-ES vs EPM5192JC Vergleich

Detaillierter Direktvergleich von EPM5192JC-ES von Intel und EPM5192JC von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5192JC-ES EPM5192JC
Marke Intel Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $16,45 $16,40
Device Family MAX 5000 —
Device Type CPLD (EPLD) —
Macrocells 192 192
Logic Array Blocks (LABs) 12 12
Interconnect Programmable Interconnect Array (PIA) —
Configuration Memory EPROM (UV-erasable, one-time programmable for JC-ES) —
Gehäuse 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84) 68-pin PLCC (JC) windowed ceramic
Montageart Surface Mount Surface Mount
Technology CMOS —
Programming Altera MAX+PLUS II or compatible programmer —
Betriebstemperatur [DATA_NEEDED: operating temperature range for ES grade] [DATA_NEEDED: commercial / industrial / military grade]
Versorgungsspannung [DATA_NEEDED: VCC nominal] [DATA_NEEDED: VCC nominal]
User I/O Pins [DATA_NEEDED: user I/O count for JC-ES in PLCC-84] —
RoHS-Status [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: original Altera marking not RoHS]
Lead-Free [DATA_NEEDED: lead-free status] —
MSL-Level [DATA_NEEDED: MSL rating] —
Note Datasheet source: Altera MAX 5000 family document, 52 pages —
Product Type — CPLD (Complex Programmable Logic Device)
Series — EPM5192 (Classic / MAX-class)
Interconnect Architecture — Programmable Interconnect Array (PIA)
Process Technology — CMOS EPROM (UV-erasable)
Programming Method — UV-erase + EPROM programmer
Non-Volatile Configuration — Yes (EPROM cell array)
Logic Family — Classic CPLD (EPM5xxx series)
Propagation Delay — [DATA_NEEDED: tpd spec by speed grade]

Datenblätter & Ressourcen

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