EPM5192JC-ES vs EPM5192JC Comparison
Detailed side-by-side comparison of EPM5192JC-ES by Intel and EPM5192JC by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192JC-ES | EPM5192JC |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Device Type | CPLD (EPLD) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Configuration Memory | EPROM (UV-erasable, one-time programmable for JC-ES) | — |
| Package | 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84) | 68-pin PLCC (JC) windowed ceramic |
| Mounting Type | Surface Mount | Surface Mount |
| Technology | CMOS | — |
| Programming | Altera MAX+PLUS II or compatible programmer | — |
| Operating Temperature | [DATA_NEEDED: operating temperature range for ES grade] | [DATA_NEEDED: commercial / industrial / military grade] |
| Supply Voltage | [DATA_NEEDED: VCC nominal] | [DATA_NEEDED: VCC nominal] |
| User I/O Pins | [DATA_NEEDED: user I/O count for JC-ES in PLCC-84] | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: original Altera marking not RoHS] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSL Level | [DATA_NEEDED: MSL rating] | — |
| Note | Datasheet source: Altera MAX 5000 family document, 52 pages | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Series | — | EPM5192 (Classic / MAX-class) |
| Interconnect Architecture | — | Programmable Interconnect Array (PIA) |
| Process Technology | — | CMOS EPROM (UV-erasable) |
| Programming Method | — | UV-erase + EPROM programmer |
| Non-Volatile Configuration | — | Yes (EPROM cell array) |
| Logic Family | — | Classic CPLD (EPM5xxx series) |
| Propagation Delay | — | [DATA_NEEDED: tpd spec by speed grade] |