EPM5192JC vs EPM5192JC2 Vergleich
Detaillierter Direktvergleich von EPM5192JC von Intel und EPM5192JC2 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192JC | EPM5192JC2 |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $16,40 | $15,90 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Series | EPM5192 (Classic / MAX-class) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| Interconnect Architecture | Programmable Interconnect Array (PIA) | — |
| Process Technology | CMOS EPROM (UV-erasable) | CMOS, UV-erasable |
| Gehäuse | 68-pin PLCC (JC) windowed ceramic | PLCC-68 (JC) |
| Montageart | Surface Mount | Surface Mount (socketable PLCC) |
| Programming Method | UV-erase + EPROM programmer | — |
| Non-Volatile Configuration | Yes (EPROM cell array) | — |
| Logic Family | Classic CPLD (EPM5xxx series) | — |
| Betriebstemperatur | [DATA_NEEDED: commercial / industrial / military grade] | — |
| Versorgungsspannung | [DATA_NEEDED: VCC nominal] | — |
| Propagation Delay | [DATA_NEEDED: tpd spec by speed grade] | — |
| RoHS-Status | [DATA_NEEDED: original Altera marking not RoHS] | — |
| Family | — | MAX 5000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates (equivalent) | — | 6000 |
| Maximum User I/O | — | 64 |
| Dedicated Inputs | — | 7 |
| External Clock Inputs | — | 1 (with shared input/clock capability) |
| Maximale Taktfrequenz | — | 50 MHz |
| Propagation Delay (tPD) | — | 45 ns (speed grade -2) |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Programming | — | Altera Master Programmer / ByteBlaster via JTAG-style interface |