EPM5192JC vs EPM5192JC2 Comparación
Comparación detallada lado a lado de EPM5192JC por Intel y EPM5192JC2 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5192JC | EPM5192JC2 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $16,40 | $15,90 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Series | EPM5192 (Classic / MAX-class) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| Interconnect Architecture | Programmable Interconnect Array (PIA) | — |
| Process Technology | CMOS EPROM (UV-erasable) | CMOS, UV-erasable |
| Encapsulado | 68-pin PLCC (JC) windowed ceramic | PLCC-68 (JC) |
| Tipo de montaje | Surface Mount | Surface Mount (socketable PLCC) |
| Programming Method | UV-erase + EPROM programmer | — |
| Non-Volatile Configuration | Yes (EPROM cell array) | — |
| Logic Family | Classic CPLD (EPM5xxx series) | — |
| Temperatura de funcionamiento | [DATA_NEEDED: commercial / industrial / military grade] | — |
| Tensión de alimentación | [DATA_NEEDED: VCC nominal] | — |
| Propagation Delay | [DATA_NEEDED: tpd spec by speed grade] | — |
| Estado RoHS | [DATA_NEEDED: original Altera marking not RoHS] | — |
| Family | — | MAX 5000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates (equivalent) | — | 6000 |
| Maximum User I/O | — | 64 |
| Dedicated Inputs | — | 7 |
| External Clock Inputs | — | 1 (with shared input/clock capability) |
| Frecuencia de reloj máxima | — | 50 MHz |
| Propagation Delay (tPD) | — | 45 ns (speed grade -2) |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Programming | — | Altera Master Programmer / ByteBlaster via JTAG-style interface |