EPM5192JC1 vs EPM5192JC68 Vergleich
Detaillierter Direktvergleich von EPM5192JC1 von Intel und EPM5192JC68 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192JC1 | EPM5192JC68 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $48,30 | $15,85 |
| Family | MAX 5000 (MAX 5xxx CPLD) | — |
| Manufacturer | Intel (formerly Altera Corporation) | — |
| Macro Cells | 192 | — |
| Usable Gates | 3750 | — |
| Maximum Operating Frequency | 62.5 MHz | — |
| Supply Voltage (VCC) | 5 V (nominal) | — |
| Process Technology | 0.5 µm CMOS, UV-erasable EPROM | — |
| Propagation Delay (typ) | [DATA_NEEDED: propagation delay in ns] | — |
| I/O Pins | [DATA_NEEDED: I/O pin count] | — |
| Gehäuse | [DATA_NEEDED: exact package from datasheet] | — |
| Montageart | [DATA_NEEDED: surface mount or through-hole] | Surface Mount (PLCC socket compatible) |
| Betriebstemperatur | [DATA_NEEDED: operating temp range] | 0C to 70C (commercial, JC suffix) |
| Programming Interface | JTAG-compatible (Altera MAX 5xxx) | — |
| Logic Blocks (LABs) | 24 (8 macrocells per LAB) | — |
| RoHS-Status | unknown | [DATA_NEEDED: RoHS compliance] |
| AEC-Q100 | not_applicable | — |
| Lifecycle | Obsolete - last-time-buy stock only at franchised distributors | — |
| Device Family | — | MAX 5000 |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Elements / Macrocells | — | 192 macrocells |
| User I/O Pins | — | 76 |
| Anzahl der Pins | — | 68 |
| Package Type | — | PLCC-68 (J-Lead) |
| Versorgungsspannung | — | [DATA_NEEDED: VCC] |
| Pin-to-Pin Delay (tPD) | — | [DATA_NEEDED: tPD] |
| Maximum Frequency (fMAX) | — | [DATA_NEEDED: fMAX] |
| Configuration Memory | — | UV-Erasable EPROM |
| Programmable Interconnect | — | Programmable Logic Array + Macrocells |
| Dedicated Inputs | — | 12 |
| Clock Pins | — | 4 dedicated |
| Programming Tool | — | MAX+PLUS II (legacy) |