EPM5192JC2 vs EPM5192JC Vergleich
Detaillierter Direktvergleich von EPM5192JC2 von Intel und EPM5192JC von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192JC2 | EPM5192JC |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $15,90 | $16,40 |
| Family | MAX 5000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| Usable Gates (equivalent) | 6000 | — |
| Maximum User I/O | 64 | — |
| Dedicated Inputs | 7 | — |
| External Clock Inputs | 1 (with shared input/clock capability) | — |
| Maximale Taktfrequenz | 50 MHz | — |
| Propagation Delay (tPD) | 45 ns (speed grade -2) | — |
| Process Technology | CMOS, UV-erasable | CMOS EPROM (UV-erasable) |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Gehäuse | PLCC-68 (JC) | 68-pin PLCC (JC) windowed ceramic |
| Montageart | Surface Mount (socketable PLCC) | Surface Mount |
| Programming | Altera Master Programmer / ByteBlaster via JTAG-style interface | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Series | — | EPM5192 (Classic / MAX-class) |
| Interconnect Architecture | — | Programmable Interconnect Array (PIA) |
| Programming Method | — | UV-erase + EPROM programmer |
| Non-Volatile Configuration | — | Yes (EPROM cell array) |
| Logic Family | — | Classic CPLD (EPM5xxx series) |
| Betriebstemperatur | — | [DATA_NEEDED: commercial / industrial / military grade] |
| Versorgungsspannung | — | [DATA_NEEDED: VCC nominal] |
| Propagation Delay | — | [DATA_NEEDED: tpd spec by speed grade] |
| RoHS-Status | — | [DATA_NEEDED: original Altera marking not RoHS] |