EPM5192JC2 vs EPM5192JC 比較
詳細な並列比較: EPM5192JC2 メーカー: Intel および EPM5192JC メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192JC2 | EPM5192JC |
|---|---|---|
| ブランド | Intel | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $15.90 | $16.40 |
| Family | MAX 5000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| Usable Gates (equivalent) | 6000 | — |
| Maximum User I/O | 64 | — |
| Dedicated Inputs | 7 | — |
| External Clock Inputs | 1 (with shared input/clock capability) | — |
| 最大クロック周波数 | 50 MHz | — |
| Propagation Delay (tPD) | 45 ns (speed grade -2) | — |
| Process Technology | CMOS, UV-erasable | CMOS EPROM (UV-erasable) |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| パッケージ | PLCC-68 (JC) | 68-pin PLCC (JC) windowed ceramic |
| 実装タイプ | Surface Mount (socketable PLCC) | Surface Mount |
| Programming | Altera Master Programmer / ByteBlaster via JTAG-style interface | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Series | — | EPM5192 (Classic / MAX-class) |
| Interconnect Architecture | — | Programmable Interconnect Array (PIA) |
| Programming Method | — | UV-erase + EPROM programmer |
| Non-Volatile Configuration | — | Yes (EPROM cell array) |
| Logic Family | — | Classic CPLD (EPM5xxx series) |
| 動作温度 | — | [DATA_NEEDED: commercial / industrial / military grade] |
| 電源電圧 | — | [DATA_NEEDED: VCC nominal] |
| Propagation Delay | — | [DATA_NEEDED: tpd spec by speed grade] |
| RoHS ステータス | — | [DATA_NEEDED: original Altera marking not RoHS] |