EPM5192JI-2 vs EPM5192LI-1 Vergleich
Detaillierter Direktvergleich von EPM5192JI-2 von Altera und EPM5192LI-1 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192JI-2 | EPM5192LI-1 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,95 | $16,40 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | EPLD (UV-Erasable/OTP Complex PLD) |
| Macrocells | 192 | 192 |
| Usable Gates | 5000 | 3,750 |
| Dedicated Inputs | 12 | — |
| Flip-Flops | 192 | — |
| Speed Grade | -2 | -1 |
| Gehäuse | JLCC-68 (J-Lead Ceramic) | — |
| Betriebstemperatur | 0C to +70C (commercial) | [DATA_NEEDED: industrial vs military range] |
| Programming Technology | UV-Erasable EPROM | — |
| Architecture | Sum-of-products with Programmable Interconnect Array (PIA) | EEPROM/EPROM-based, non-volatile, instant-on |
| Versorgungsspannung | 5 V (typical) | 5 V |
| Process Technology | CMOS EPROM | CMOS EPROM, UV-erasable |
| Montageart | Surface Mount | Surface Mount (JLCC with J-leads) |
| RoHS-Status | Non-compliant (ceramic JLCC, contains lead) | [DATA_NEEDED: RoHS status of ceramic LI variant] |
| Lebenszyklusstatus | Obsolete (legacy Altera MAX 5000 family) | — |
| Maximum Toggle Frequency | — | 40 MHz |
| Propagation Delay (tPD) | — | [DATA_NEEDED: tPD in ns at -1 grade] |
| User I/O Pins | — | [DATA_NEEDED: user I/O count for JLCC variant] |
| Package Type | — | JLCC (windowed, ceramic, UV-erasable) |
| Pin-Anzahl | — | [DATA_NEEDED: pin count of LI package] |
| MSL-Level | — | [DATA_NEEDED: MSL level] |
| Lead Free | — | [DATA_NEEDED: lead-free] |
| Programmable Interconnect | — | Programmable Interconnect Array (PIA) |