EPM5192JI vs EPM5192JC Vergleich
Detaillierter Direktvergleich von EPM5192JI von Altera und EPM5192JC von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192JI | EPM5192JC |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,75 | $16,40 |
| Family | MAX 5000 | — |
| Device Type | EPLD (UV-erasable CMOS Programmable Logic Device) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | — |
| Propagation Delay (tpd) | 55 ns | — |
| Versorgungsspannung | 4.75 V to 5.25 V (nominal 5 V) | [DATA_NEEDED: VCC nominal] |
| Technology | CMOS EPROM, UV-erasable | — |
| Gehäuse | 84-pin PLCC (windowed, J-suffix ceramic) | 68-pin PLCC (JC) windowed ceramic |
| Betriebstemperatur | -40 C to +125 C (industrial, I-suffix) | [DATA_NEEDED: commercial / industrial / military grade] |
| Montageart | Surface Mount (PLCC socket recommended for UV erasure) | Surface Mount |
| RoHS-Status | [DATA_NEEDED: RoHS status - pre-2010 part, likely non-compliant] | [DATA_NEEDED: original Altera marking not RoHS] |
| Programming Method | Altera MAX 5000 programming algorithm (device programmer) | UV-erase + EPROM programmer |
| Erasure Method | UV exposure through windowed package | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Series | — | EPM5192 (Classic / MAX-class) |
| Interconnect Architecture | — | Programmable Interconnect Array (PIA) |
| Process Technology | — | CMOS EPROM (UV-erasable) |
| Non-Volatile Configuration | — | Yes (EPROM cell array) |
| Logic Family | — | Classic CPLD (EPM5xxx series) |
| Propagation Delay | — | [DATA_NEEDED: tpd spec by speed grade] |