EPM5192LC vs EPM5192GM Vergleich

Detaillierter Direktvergleich von EPM5192LC von Altera und EPM5192GM von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5192LC EPM5192GM
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $28,40 $58,00
Family MAX 7000S —
Macrocells 192 —
Logic Array Blocks (LABs) 12 —
User I/O Pins 64 —
Dedicated Inputs 7 —
Global Clock Inputs 1 —
Propagation Delay (tPD) 55 ns (typical, commercial) —
Maximum Clock Frequency (fMAX) 50 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V (nominal 5 V) —
Process Technology CMOS, UV-erasable/OTP EPROM configuration —
Programmable Interconnect Programmable Interconnect Array (PIA), fixed delay —
Boundary-Scan Support JTAG IEEE 1149.1 —
Programming Interface JTAG (ByteBlaster-compatible) JTAG-compatible (per MAX 5000 family)
Operating Temperature (commercial) 0C to +70C —
Gehäuse JLCC-68 (windowed ceramic, LC suffix) CPGA-84 (Ceramic Pin Grid Array, 84 pins, windowed)
Montageart Surface Mount Through-Hole (PGA)
RoHS-Status [DATA_NEEDED: RoHS status] Non-compliant (contains lead in ceramic PGA)
Product Family — MAX 5000
Device Type — UV Erasable Programmable Logic Device (PLD)
Technology — CMOS
Number of Macrocells — 192
Usable Gates — 3,750
Pin-to-Pin Delay (tPD) — 15 ns (fastest speed grade); 55 ns (this part)
Counter Frequency (fCNT) — up to 76.9 MHz
Propagation Delay (tPD, this part) — 55 ns
Erasure Method — UV (windowed ceramic package)
Versorgungsspannung — [DATA_NEEDED: typical VCC range]
Maximum User I/O — [DATA_NEEDED: exact I/O count for CPGA-84]
Betriebstemperatur — [DATA_NEEDED: commercial/industrial/military grade]
Process Node — [DATA_NEEDED: CMOS process geometry]

Datenblätter & Ressourcen

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