EPM5192LC1 vs EPM5192JC Vergleich
Detaillierter Direktvergleich von EPM5192LC1 von Altera und EPM5192JC von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192LC1 | EPM5192JC |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $17,40 | $16,40 |
| Family | MAX 5000 | — |
| Device Type | Complex PLD (CPLD), UV-erasable/OTP | — |
| Macrocells | 192 | 192 |
| Equivalent Gates | 3750 | — |
| Dedicated Inputs | 7 | — |
| User I/O Pins | 64 | — |
| Gehäuse | PQCC-84 (JEDEC S-PQCC-J84, 84-lead Plastic Leaded Chip Carrier) | 68-pin PLCC (JC) windowed ceramic |
| Nominal Supply Voltage (VCC) | 5 V | — |
| Supply Voltage Range | 4.75 V to 5.25 V | — |
| Maximale Taktfrequenz | 50 MHz | — |
| Propagation Delay (tPD) | 40 ns | — |
| Process Technology | CMOS EPROM | CMOS EPROM (UV-erasable) |
| Programming Method | OTP (LC plastic package); UV-erasable equivalents in JC ceramic package | UV-erase + EPROM programmer |
| Operating Temperature (Commercial 'LC') | 0 °C to 70 °C | — |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: original Altera marking not RoHS] |
| JEDEC Package Code | S-PQCC-J84 | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Series | — | EPM5192 (Classic / MAX-class) |
| Logic Array Blocks (LABs) | — | 12 |
| Interconnect Architecture | — | Programmable Interconnect Array (PIA) |
| Non-Volatile Configuration | — | Yes (EPROM cell array) |
| Logic Family | — | Classic CPLD (EPM5xxx series) |
| Betriebstemperatur | — | [DATA_NEEDED: commercial / industrial / military grade] |
| Versorgungsspannung | — | [DATA_NEEDED: VCC nominal] |
| Propagation Delay | — | [DATA_NEEDED: tpd spec by speed grade] |