EPM5192LC2 vs EPM5192LC-25 Vergleich

Detaillierter Direktvergleich von EPM5192LC2 von Intel und EPM5192LC-25 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5192LC2 EPM5192LC-25
Marke Intel Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $17,40 $55,00
Family MAX 5000 MAX 5000
Device Type EPLD (Erasable Programmable Logic Device) —
Macrocells 192 192
User I/O Pins 64 —
Logic Array Blocks (LABs) 12 —
Dedicated Inputs 7 —
External Clock Inputs 1 —
Propagation Delay (tpd) 45 ns (LC-2 speed grade) —
Maximale Taktfrequenz 50 MHz —
Supply Voltage (VCC) 5 V —
Process Technology CMOS —
Gehäuse PQCC-84 (84-pin Plastic J-Lead Chip Carrier) JLCC-84 (ceramic J-lead chip carrier)
Montageart Surface Mount Surface Mount
Betriebstemperatur [DATA_NEEDED: operating temperature range] 0C to +70C (commercial)
Programmable Interconnect Programmable Interconnect Array (PIA) —
Reprogrammability Windowed UV-erasable (ceramic package variants) / One-time programmable (plastic) —
Product Type — CPLD (Complex Programmable Logic Device)
Logic Elements — 192 (1 macrocell ≈ 1 LE in MAX 5000 architecture)
Pin-to-Pin Delay (tPD) — 25 ns
Speed Grade — -25 (25 ns)
Programmable Technology — UV-erasable / OTP (EPROM-based)
Programming Interface — JTAG / Altera programming hardware (legacy)
Versorgungsspannung — 5 V (typical, MAX 5000)
I/O Standard — TTL-compatible
Configuration Memory — Non-volatile EPROM (on-chip)
Manufacturer — Altera Corporation (now Intel PSG)
RoHS-Status — Unknown (legacy ceramic package typically non-RoHS)

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