EPM5192LC84-1 vs EPM5192LC84-2 Vergleich
Detaillierter Direktvergleich von EPM5192LC84-1 von Altera und EPM5192LC84-2 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192LC84-1 | EPM5192LC84-2 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $21,85 | $7,10 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (UV-Erasable / OTP Complex PLD) | EPLD (UV-Erasable / OTP Complex PLD) |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 16 | — |
| Usable Gates | 7,500 | — |
| Speed Grade | -1 | -2 |
| Propagation Delay (tPD) | [DATA_NEEDED: tPD ns value] | — |
| Supply Voltage (VCC) | 5 V | — |
| Program Memory Type | UV-EPROM / OTP | — |
| Gehäuse | 84-pin PLCC (LC84) | 84-pin PLCC (LC) |
| Montageart | Surface Mount (J-lead) | Surface Mount |
| Betriebstemperatur | 0C to +70C (commercial) | Commercial (0C to +70C) |
| I/O Count | [DATA_NEEDED: I/O pin count] | — |
| RoHS-Status | [DATA_NEEDED: not stated in provided data] | Non-compliant (SnPb lead finish typical for this vintage) |
| Process Technology | CMOS EPROM | — |
| Versorgungsspannung | — | 5 V (TTL-compatible I/O) |
| Technology | — | CMOS, UV-erasable / OTP |
| Logic Elements | — | AND-OR array with macrocell flip-flops |
| Programming Method | — | Altera legacy programmer (JEDEC bitstream) |
| Lebenszyklusstatus | — | Obsolete (last Altera MAX 5000 production) |
| JTAG Support | — | Vendor-specific programming interface (pre-IEEE 1532) |
| I/O Standard | — | TTL, 5V CMOS-compatible |