EPM5192LI-1 vs EPM5192JI Vergleich

Detaillierter Direktvergleich von EPM5192LI-1 von Altera und EPM5192JI von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5192LI-1 EPM5192JI
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus NRND Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $16,40 $9,75
Family MAX 5000 MAX 5000
Device Type EPLD (UV-Erasable/OTP Complex PLD) EPLD (UV-erasable CMOS Programmable Logic Device)
Usable Gates 3,750 —
Macrocells 192 192
Maximum Toggle Frequency 40 MHz —
Versorgungsspannung 5 V 4.75 V to 5.25 V (nominal 5 V)
Propagation Delay (tPD) [DATA_NEEDED: tPD in ns at -1 grade] —
User I/O Pins [DATA_NEEDED: user I/O count for JLCC variant] 64
Package Type JLCC (windowed, ceramic, UV-erasable) —
Process Technology CMOS EPROM, UV-erasable —
Speed Grade -1 —
Betriebstemperatur [DATA_NEEDED: industrial vs military range] -40 C to +125 C (industrial, I-suffix)
Pin-Anzahl [DATA_NEEDED: pin count of LI package] —
Montageart Surface Mount (JLCC with J-leads) Surface Mount (PLCC socket recommended for UV erasure)
MSL-Level [DATA_NEEDED: MSL level] —
RoHS-Status [DATA_NEEDED: RoHS status of ceramic LI variant] [DATA_NEEDED: RoHS status - pre-2010 part, likely non-compliant]
Lead Free [DATA_NEEDED: lead-free] —
Programmable Interconnect Programmable Interconnect Array (PIA) —
Architecture EEPROM/EPROM-based, non-volatile, instant-on —
Logic Array Blocks (LABs) — 12
Dedicated Inputs — 7
Propagation Delay (tpd) — 55 ns
Technology — CMOS EPROM, UV-erasable
Gehäuse — 84-pin PLCC (windowed, J-suffix ceramic)
Programming Method — Altera MAX 5000 programming algorithm (device programmer)
Erasure Method — UV exposure through windowed package

Datenblätter & Ressourcen

Alle Produkte durchsuchen BOM erstellen Angebot anfordern