EPM5192LI-1 vs EPM5192JI 비교
다음의 상세 나란히 비교: EPM5192LI-1 제조: Altera 및 EPM5192JI 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM5192LI-1 | EPM5192JI |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | NRND | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $16.40 | $9.75 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (UV-Erasable/OTP Complex PLD) | EPLD (UV-erasable CMOS Programmable Logic Device) |
| Usable Gates | 3,750 | — |
| Macrocells | 192 | 192 |
| Maximum Toggle Frequency | 40 MHz | — |
| 공급 전압 | 5 V | 4.75 V to 5.25 V (nominal 5 V) |
| Propagation Delay (tPD) | [DATA_NEEDED: tPD in ns at -1 grade] | — |
| User I/O Pins | [DATA_NEEDED: user I/O count for JLCC variant] | 64 |
| Package Type | JLCC (windowed, ceramic, UV-erasable) | — |
| Process Technology | CMOS EPROM, UV-erasable | — |
| Speed Grade | -1 | — |
| 동작 온도 | [DATA_NEEDED: industrial vs military range] | -40 C to +125 C (industrial, I-suffix) |
| 핀 수 | [DATA_NEEDED: pin count of LI package] | — |
| 실장 유형 | Surface Mount (JLCC with J-leads) | Surface Mount (PLCC socket recommended for UV erasure) |
| MSL 레벨 | [DATA_NEEDED: MSL level] | — |
| RoHS 상태 | [DATA_NEEDED: RoHS status of ceramic LI variant] | [DATA_NEEDED: RoHS status - pre-2010 part, likely non-compliant] |
| Lead Free | [DATA_NEEDED: lead-free] | — |
| Programmable Interconnect | Programmable Interconnect Array (PIA) | — |
| Architecture | EEPROM/EPROM-based, non-volatile, instant-on | — |
| Logic Array Blocks (LABs) | — | 12 |
| Dedicated Inputs | — | 7 |
| Propagation Delay (tpd) | — | 55 ns |
| Technology | — | CMOS EPROM, UV-erasable |
| 패키지 | — | 84-pin PLCC (windowed, J-suffix ceramic) |
| Programming Method | — | Altera MAX 5000 programming algorithm (device programmer) |
| Erasure Method | — | UV exposure through windowed package |