EPM5192LI-1 vs EPM5192JI-1 Vergleich
Detaillierter Direktvergleich von EPM5192LI-1 von Altera und EPM5192JI-1 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192LI-1 | EPM5192JI-1 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $16,40 | $17,40 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (UV-Erasable/OTP Complex PLD) | CMOS UV-Erasable Programmable Logic Device (PLD / EPLD) |
| Usable Gates | 3,750 | — |
| Macrocells | 192 | 192 |
| Maximum Toggle Frequency | 40 MHz | — |
| Versorgungsspannung | 5 V | — |
| Propagation Delay (tPD) | [DATA_NEEDED: tPD in ns at -1 grade] | 55 ns |
| User I/O Pins | [DATA_NEEDED: user I/O count for JLCC variant] | 64 |
| Package Type | JLCC (windowed, ceramic, UV-erasable) | — |
| Process Technology | CMOS EPROM, UV-erasable | CMOS EPROM |
| Speed Grade | -1 | -1 (slowest grade in EPM5192 family) |
| Betriebstemperatur | [DATA_NEEDED: industrial vs military range] | Industrial, -40 C to +85 C |
| Pin-Anzahl | [DATA_NEEDED: pin count of LI package] | — |
| Montageart | Surface Mount (JLCC with J-leads) | — |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| RoHS-Status | [DATA_NEEDED: RoHS status of ceramic LI variant] | [DATA_NEEDED: RoHS compliance] |
| Lead Free | [DATA_NEEDED: lead-free] | — |
| Programmable Interconnect | Programmable Interconnect Array (PIA) | — |
| Architecture | EEPROM/EPROM-based, non-volatile, instant-on | — |
| Logic Array Blocks (LABs) | — | 12 |
| Dedicated Inputs | — | 7 |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V (nominal 5 V) |
| Gehäuse | — | 84-pin JLCC (Windowed ceramic J-lead) |
| Configuration Memory | — | UV-erasable EPROM |
| Programming Method | — | External EPROM programmer (via programming hardware) |
| Logic Element per Macrocell | — | 1 D flip-flop + AND/OR array |