EPM5192LI-1 vs EPM5192JI-1 比較
詳細な並列比較: EPM5192LI-1 メーカー: Altera および EPM5192JI-1 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192LI-1 | EPM5192JI-1 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $16.40 | $17.40 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (UV-Erasable/OTP Complex PLD) | CMOS UV-Erasable Programmable Logic Device (PLD / EPLD) |
| Usable Gates | 3,750 | — |
| Macrocells | 192 | 192 |
| Maximum Toggle Frequency | 40 MHz | — |
| 電源電圧 | 5 V | — |
| Propagation Delay (tPD) | [DATA_NEEDED: tPD in ns at -1 grade] | 55 ns |
| User I/O Pins | [DATA_NEEDED: user I/O count for JLCC variant] | 64 |
| Package Type | JLCC (windowed, ceramic, UV-erasable) | — |
| Process Technology | CMOS EPROM, UV-erasable | CMOS EPROM |
| Speed Grade | -1 | -1 (slowest grade in EPM5192 family) |
| 動作温度 | [DATA_NEEDED: industrial vs military range] | Industrial, -40 C to +85 C |
| ピン数 | [DATA_NEEDED: pin count of LI package] | — |
| 実装タイプ | Surface Mount (JLCC with J-leads) | — |
| MSLレベル | [DATA_NEEDED: MSL level] | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status of ceramic LI variant] | [DATA_NEEDED: RoHS compliance] |
| Lead Free | [DATA_NEEDED: lead-free] | — |
| Programmable Interconnect | Programmable Interconnect Array (PIA) | — |
| Architecture | EEPROM/EPROM-based, non-volatile, instant-on | — |
| Logic Array Blocks (LABs) | — | 12 |
| Dedicated Inputs | — | 7 |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V (nominal 5 V) |
| パッケージ | — | 84-pin JLCC (Windowed ceramic J-lead) |
| Configuration Memory | — | UV-erasable EPROM |
| Programming Method | — | External EPROM programmer (via programming hardware) |
| Logic Element per Macrocell | — | 1 D flip-flop + AND/OR array |