EPM570GT100C5N vs EPM570GT100I5 Vergleich
Detaillierter Direktvergleich von EPM570GT100C5N von Intel und EPM570GT100I5 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM570GT100C5N | EPM570GT100I5 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $11,05 | $4,95 |
| Series | MAX II | MAX II |
| Logic Elements | 570 | — |
| Equivalent Macrocells | 440 | — |
| User I/O | 76 | — |
| LABs | 36 | — |
| Maximum Frequency | 304 MHz | — |
| Pin-to-Pin Delay | [DATA_NEEDED: tPD value] | — |
| User Flash Memory (UFM) | 8 Kbit | — |
| Operating Supply Voltage (VCCINT) | 2.5 V / 3.3 V | — |
| I/O Standards Supported | 1.5 V, 1.8 V, 2.5 V, 3.3 V LVTTL/LVCMOS | — |
| Gehäuse | TQFP-100 | 100-pin TQFP (14x14 mm, 0.5 mm pitch) |
| Montageart | Surface Mount | Surface Mount (Gull-wing leads) |
| Betriebstemperatur | 0C to +85C (Commercial) | -40 C to +100 C (Industrial, "I5") |
| Programmability | Flash-based, non-volatile (ISP via JTAG) | In-System Programmable (ISP) via JTAG, non-volatile flash |
| JTAG Support | IEEE 1149.1 boundary scan | IEEE 1149.1 boundary scan |
| RoHS-Status | Compliant | Compliant |
| Logic Elements (LE) | — | 570 |
| Macrocells | — | 440 |
| Maximum User I/O Pins | — | 76 |
| Propagation Delay (tPD) | — | 5.4 ns (typ) |
| Internal Supply Voltage (VCCINT) | — | 1.71 V to 1.89 V |
| User I/O Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| User Flash Memory | — | 8 Kbits |
| Configuration Time | — | Instant-On (< 1 ms, no external PROM required) |
| Typical Active Current | — | [DATA_NEEDED: typical active ICC] |
| Speed Grade | — | GT (fast) |
| Global Clock Networks | — | 4 |