EPM570GT100C5N vs EPM570GT100I5 比較
詳細な並列比較: EPM570GT100C5N メーカー: Intel および EPM570GT100I5 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM570GT100C5N | EPM570GT100I5 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $11.05 | $4.95 |
| Series | MAX II | MAX II |
| Logic Elements | 570 | — |
| Equivalent Macrocells | 440 | — |
| User I/O | 76 | — |
| LABs | 36 | — |
| Maximum Frequency | 304 MHz | — |
| Pin-to-Pin Delay | [DATA_NEEDED: tPD value] | — |
| User Flash Memory (UFM) | 8 Kbit | — |
| Operating Supply Voltage (VCCINT) | 2.5 V / 3.3 V | — |
| I/O Standards Supported | 1.5 V, 1.8 V, 2.5 V, 3.3 V LVTTL/LVCMOS | — |
| パッケージ | TQFP-100 | 100-pin TQFP (14x14 mm, 0.5 mm pitch) |
| 実装タイプ | Surface Mount | Surface Mount (Gull-wing leads) |
| 動作温度 | 0C to +85C (Commercial) | -40 C to +100 C (Industrial, "I5") |
| Programmability | Flash-based, non-volatile (ISP via JTAG) | In-System Programmable (ISP) via JTAG, non-volatile flash |
| JTAG Support | IEEE 1149.1 boundary scan | IEEE 1149.1 boundary scan |
| RoHS ステータス | Compliant | Compliant |
| Logic Elements (LE) | — | 570 |
| Macrocells | — | 440 |
| Maximum User I/O Pins | — | 76 |
| Propagation Delay (tPD) | — | 5.4 ns (typ) |
| Internal Supply Voltage (VCCINT) | — | 1.71 V to 1.89 V |
| User I/O Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| User Flash Memory | — | 8 Kbits |
| Configuration Time | — | Instant-On (< 1 ms, no external PROM required) |
| Typical Active Current | — | [DATA_NEEDED: typical active ICC] |
| Speed Grade | — | GT (fast) |
| Global Clock Networks | — | 4 |