EPM570T10015 vs EPM570T100C5 Vergleich
Detaillierter Direktvergleich von EPM570T10015 von Altera und EPM570T100C5 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM570T10015 | EPM570T100C5 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,95 | $7,10 |
| Device Family | MAX II | — |
| Logic Elements | 570 | 570 |
| Macro Cells | 440 | — |
| User Flash Memory | 8 Kbits | 8 Kbits |
| Maximum User I/O Pins | 76 | 76 |
| Gehäuse | TQFP-100 (T100) 14 x 14 mm | TQFP-100 (14x14 mm) |
| Pin-to-Pin Delay (tPD) | 15 ns (commercial/industrial speed grade) | — |
| Propagation Delay | [DATA_NEEDED: detailed tPD/tCO/tSU datasheet values] | — |
| Supply Voltage - Core (VCCINT) | 3.3 V (2.5 V variants exist in MAX II family) | — |
| Supply Voltage - I/O (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (multi-volt I/O) | — |
| Betriebstemperaturbereich | -40 °C to +85 °C (industrial) | — |
| Configuration Memory | On-chip flash (non-volatile, instant-on) | — |
| Programming Interface | JTAG (IEEE 1149.1 / IEEE Std 1532) | JTAG (IEEE 1149.1) ISP |
| Supported I/O Standards | LVTTL, LVCMOS, PCI, SSTL (per pin) | — |
| Process Technology | 0.18 µm | 0.18 µm |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | Compliant |
| MSL-Level | [DATA_NEEDED: moisture sensitivity level] | — |
| Series | — | MAX II |
| Family | — | MAX II CPLD |
| Macrocells | — | 440 |
| Propagation Delay (tpd) | — | 5.4 ns (max) |
| Maximum Frequency | — | 201.1 MHz |
| Internal Supply Voltage | — | 2.5 V / 3.3 V |
| I/O Voltage Support | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Montageart | — | Surface Mount |
| Betriebstemperatur | — | 0°C to 85°C (TJ) |