EPM7096QI100-15 vs EPM7096QC100-10 Vergleich
Detaillierter Direktvergleich von EPM7096QI100-15 von Altera und EPM7096QC100-10 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM7096QI100-15 - MAX 7000 CPLD 96 Macro 76 I/O 15ns | Altera
EPM7096QI100-15 ⚠ Letzte BestellmöglichkeitAltera
EPM7096QC100-10 - 96-Macrocell MAX 7000 CPLD, 10ns, PQFP-100 | Altera
EPM7096QC100-10 ObsoleteSpezifikationsvergleich
| Parameter | EPM7096QI100-15 | EPM7096QC100-10 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $14,20 | $7,10 |
| Series | MAX 7000 | — |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Programmable Type | EE PLD (EEPROM-based, in-system programmable) | — |
| Number of Macrocells | 96 | — |
| Number of Logic Array Blocks (LABs) | 4 | — |
| Number of Usable Gates | 1,800 | — |
| Number of I/O Pins | 76 | — |
| Maximum Propagation Delay (tPD) | 15 ns | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | 4.75 V to 5.25 V |
| Betriebstemperatur | -40C to +85C (industrial, per Q-suffix) | 0 °C to +70 °C (commercial) |
| Gehäuse / Bauform | 100-BQFP (BQFP-100) | — |
| Montageart | Surface Mount | Surface Mount |
| Programming Interface | IEEE Std. 1149.1 JTAG (ISP) | ByteBlaster / parallel (JTAG ISP on MAX 7000S variants) |
| Packaging | Tray | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status not stated in verified data] | [DATA_NEEDED: RoHS compliance status] |
| Family | — | MAX 7000 |
| Macrocells | — | 96 |
| Logic Array Blocks | — | 4 |
| User I/O Pins | — | 76 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Operating Frequency | — | 100 MHz |
| Technology | — | EEPROM-based CMOS |
| Boundary Scan | — | IEEE Std. 1149.1 (JTAG) on MAX 7000S |
| PCI Compliance | — | Yes (PCI SIG Local Bus Specification Rev. 2.2 at -10 speed grade) |
| Gehäuse | — | 100-pin PQFP (R-PQFP-G100, 20×14 mm, 0.65 mm pitch) |