EPM7096QI100-15 vs EPM7096QC100-10 对比

详细并排对比 EPM7096QI100-15 出自 Altera 和 EPM7096QC100-10 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM7096QI100-15 EPM7096QI100-15 - MAX 7000 CPLD 96 Macro 76 I/O 15ns | Altera

EPM7096QI100-15 - MAX 7000 CPLD 96 Macro 76 I/O 15ns | Altera

EPM7096QI100-15 ⚠ 最后一次采购

规格对比

参数 EPM7096QI100-15 EPM7096QC100-10
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 Obsolete
库存状态 有库存 有库存
单价(USD) $14.20 $7.10
Series MAX 7000 —
Device Type CPLD - Complex Programmable Logic Device —
Programmable Type EE PLD (EEPROM-based, in-system programmable) —
Number of Macrocells 96 —
Number of Logic Array Blocks (LABs) 4 —
Number of Usable Gates 1,800 —
Number of I/O Pins 76 —
Maximum Propagation Delay (tPD) 15 ns —
Supply Voltage (VCC) 4.5 V to 5.5 V 4.75 V to 5.25 V
工作温度 -40C to +85C (industrial, per Q-suffix) 0 °C to +70 °C (commercial)
封装 / 外壳 100-BQFP (BQFP-100) —
安装类型 Surface Mount Surface Mount
Programming Interface IEEE Std. 1149.1 JTAG (ISP) ByteBlaster / parallel (JTAG ISP on MAX 7000S variants)
Packaging Tray —
RoHS 状态 [DATA_NEEDED: RoHS compliance status not stated in verified data] [DATA_NEEDED: RoHS compliance status]
Family — MAX 7000
Macrocells — 96
Logic Array Blocks — 4
User I/O Pins — 76
Propagation Delay (tPD) — 10 ns
Maximum Operating Frequency — 100 MHz
Technology — EEPROM-based CMOS
Boundary Scan — IEEE Std. 1149.1 (JTAG) on MAX 7000S
PCI Compliance — Yes (PCI SIG Local Bus Specification Rev. 2.2 at -10 speed grade)
封装 — 100-pin PQFP (R-PQFP-G100, 20×14 mm, 0.65 mm pitch)

数据手册与资源

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