EPM7128ATC144-10 vs EPM7128AETC144-7N Vergleich
Detaillierter Direktvergleich von EPM7128ATC144-10 von Altera und EPM7128AETC144-7N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM7128AETC144-7N - MAX 7000A CPLD, 128 Macros, 144-TQFP | Intel / Altera
EPM7128AETC144-7N ✓ AktivSpezifikationsvergleich
| Parameter | EPM7128ATC144-10 | EPM7128AETC144-7N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,10 | $39,82 |
| Manufacturer | Altera (now Intel) | — |
| Series | MAX 7000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Programmable Type | EE PLD (EEPROM-based, in-system programmable) | — |
| Macrocells | 128 | — |
| Logic Array Blocks | 4 | — |
| User I/O Pins | 68 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 98 MHz | — |
| Supply Voltage - Internal (VCCINT) | 3.0 V to 3.6 V | — |
| I/O Voltage Levels | 5.0 V / 3.3 V / 2.5 V compatible (MultiVolt I/O) | — |
| In-System Programmability | Yes (IEEE Std 1149.1 JTAG) | — |
| Betriebstemperatur | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Gehäuse / Bauform | 144-TQFP (20 x 20 mm) | — |
| Montageart | Surface Mount | Surface Mount |
| Architecture | Multiple Array Matrix (MAX), 2nd generation | — |
| RoHS-Status | unknown (legacy Altera device) | Compliant |
| Family | — | MAX 7000A |
| Logic Gates | — | 2500 (2.5K gates) |
| Macro Cells | — | 128 |
| User I/Os | — | 36 (in 144-pin TQFP) |
| Maximum Operating Frequency | — | 129.9 MHz |
| Pin-to-Pin Delay | — | 7.5 ns |
| Propagation Delay (tpd) | — | 7.5 ns |
| Supply Voltage (VCCINT) | — | 3.3 V |
| Process Technology | — | CMOS, EEPROM-based |
| Programmability | — | In-System Programmable (ISP) via JTAG |
| Boundary-Scan Test | — | IEEE Std 1149.1 (JTAG) |
| Gehäuse | — | 144-pin TQFP |
| Pin-Compatible With | — | MAX 7000S 5.0V family (144-pin TQFP) |
| Lead-Free | — | Yes |