EPM7128ELC84-12 vs EPM7096LC84-15 Vergleich
Detaillierter Direktvergleich von EPM7128ELC84-12 von Altera und EPM7096LC84-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM7128ELC84-12 | EPM7096LC84-15 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $10,40 | $9,85 |
| Family | MAX 7000 (MAX 7000E series) | MAX 7000 |
| Logic Family | CMOS, EEPROM-based | — |
| Usable Gates | 2,500 | 1,800 |
| Macrocells | 128 | — |
| Logic Array Blocks (LABs) | 8 | 4 |
| User I/Os | 84 | — |
| Propagation Delay (tpd1) | 12 ns | — |
| Internal Global Clock Frequency | 90.9 MHz | — |
| Setup Time | 4.5 ns | — |
| Supply Voltage (VCCINT / VCCIO) | 5 V (4.75 V to 5.25 V) | — |
| Betriebstemperatur | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Gehäuse | 84-pin PLCC (J-Lead, QCCJ) | — |
| Montageart | Surface Mount (PLCC socket compatible) | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | IEEE Std. 1149.1 JTAG |
| Pin-Anzahl | 84 | — |
| RoHS-Status | Non-compliant (legacy 5V part, SnPb finish) | [DATA_NEEDED: RoHS compliance status] |
| Series | — | MAX 7000 (second-generation MAX architecture) |
| Macro Cells | — | 96 |
| Pin-to-Pin Propagation Delay (tPD) | — | 15 ns |
| Maximum Operating Frequency | — | 76.9 MHz |
| User I/O Pins | — | 68 (36 per LAB, [DATA_NEEDED: exact LAB-level split]) |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Programmable Type | — | EE PLD (in-system programmable via JTAG) |
| Gehäuse / Bauform | — | 84-PLCC (J-Lead) |
| Supplier Device Package | — | 84-PLCC (29.31 x 29.31 mm) |
| Data Retention | — | [DATA_NEEDED: data retention years] |
| Erase/Program Endurance | — | [DATA_NEEDED: erase/program cycle count] |