EPM7128SLI84-10N vs EPM7128ELI84-20 Vergleich
Detaillierter Direktvergleich von EPM7128SLI84-10N von Altera und EPM7128ELI84-20 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM7128SLI84-10N - MAX 7000S CPLD 128 Macro 10ns 84-PLCC | Intel / Altera
EPM7128SLI84-10N NrndIntel
EPM7128ELI84-20 - 128-Macrocell CPLD, 20ns, 84-PLCC | Intel / Altera
EPM7128ELI84-20 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPM7128SLI84-10N | EPM7128ELI84-20 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $8,45 | $7,95 |
| Family | MAX 7000S | MAX 7000 (Classic / MAX 7000B/E) |
| Logic Cells / Macro Cells | 128 macro cells | — |
| Usable Gates | 2,500 | 2,500 |
| Number of Logic Elements / Blocks | 16 Logic Array Blocks (LABs) | — |
| User I/Os | 68 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Frequency (fMAX) | 125 MHz | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5 V typical) | 5 V (4.75 V to 5.25 V for -20 speed grade) |
| I/O Voltage Tolerance | 3.3 V / 5 V MultiVolt I/O | — |
| Process Technology | CMOS EEPROM | — |
| Programmability | In-system programmable (ISP), non-volatile EEPROM | — |
| Boundary-Scan (JTAG) | IEEE Std 1149.1 compliant | — |
| Gehäuse | 84-pin PLCC (J-Lead) | 84-pin PLCC (J-Lead) |
| Montageart | Surface Mount | Surface Mount / Socketable (PLCC J-Lead) |
| Betriebstemperatur | -40 C to +85 C (Industrial) | -40 °C to +85 °C (Industrial) |
| RoHS-Status | [DATA_NEEDED: RoHS compliance per latest Intel/Altera declaration] | Compliant (lead-free PLCC variant) |
| Lead-Free | [DATA_NEEDED: lead-free per latest Intel/Altera declaration] | — |
| Device Name | — | EPM7128E |
| Macro Cells | — | 128 |
| Logic Array Blocks (LABs) | — | 8 |
| Maximum User I/Os | — | 68 |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Maximum Operating Frequency (fCNT) | — | 62.5 MHz |
| Programming Interface | — | JTAG (IEEE 1149.1) + ISP |
| Technology | — | EEPROM-based CMOS |