EPM7128STC100-6 vs EPM7128STC100-10 Vergleich
Detaillierter Direktvergleich von EPM7128STC100-6 von Intel und EPM7128STC100-10 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM7128STC100-10 - 128-Macro MAX 7000S CPLD, 10ns TQFP-100 | Intel / Altera
EPM7128STC100-10 ObsoleteSpezifikationsvergleich
| Parameter | EPM7128STC100-6 | EPM7128STC100-10 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $5,20 | $7,10 |
| Family | MAX 7000S | MAX 7000S |
| Macrocells | 128 | — |
| Equivalent Gates | 2,500 | — |
| User I/O Pins | 84 | — |
| Pin-to-Pin Delay (tPD) | 6 ns | — |
| Maximum Internal Frequency (fCNT) | 147.1 MHz | — |
| Supply Voltage (VCCINT / VCCIO) | 5 V | — |
| Gehäuse | 100-pin TQFP (STC100) | TQFP-100 (C100) |
| Montageart | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE Std. 1149.1) / ISP | — |
| Betriebstemperatur | 0C to +70C (commercial) | 0C to +70C (commercial) |
| PCI Compliance | 33 MHz PCI Local Bus Rev. 2.2 (-6/-7/-10 grades) | — |
| Lead Pitch | 1.0 mm (TQFP) | — |
| Lead-Free / RoHS | Contains lead (non-RoHS original; -6N variant is lead-free) | — |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 128 |
| Usable Gates | — | 2,500 |
| User I/Os | — | 84 |
| Logic Array Blocks | — | 8 (16 macrocells per LAB) |
| Propagation Delay (tPD) | — | 10 ns |
| Internal Counter Frequency (fCNT) | — | 100 MHz |
| Logic Family | — | CMOS |
| Supply Voltage (VCCINT) | — | 5 V |
| MultiVolt I/O Voltage | — | 3.3 V / 5 V |
| Pin-Anzahl | — | 100 |
| Programmability | — | In-System Programmable (JTAG, IEEE 1149.1), EEPROM |
| RoHS-Status | — | [DATA_NEEDED: RoHS compliance status not in provided data] |