EPM7160EQC100-20 vs EPM7160STI100-10 Vergleich
Detaillierter Direktvergleich von EPM7160EQC100-20 von Altera und EPM7160STI100-10 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM7160EQC100-20 - MAX 7000 CPLD, 160 Macrocells, 100-Pin PQFP
EPM7160EQC100-20 ⚠ Letzte Bestellmöglichkeit
Spezifikationsvergleich
| Parameter | EPM7160EQC100-20 | EPM7160STI100-10 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $17,10 | $90,43 |
| Series | MAX 7000 | — |
| Family | MAX 7000 CPLD | MAX 7000S |
| Architecture | CMOS EEPROM-based, non-volatile | — |
| Usable Gates | 3,200 | 3,200 |
| Macrocells | 160 | 160 |
| Logic Array Blocks (LABs) | 10 | — |
| Maximum User I/Os | 84 | — |
| Pin-to-Pin Propagation Delay (tPD) | 20 ns | — |
| Maximum Internal Frequency (fCNT) | 62.5 MHz | — |
| Supply Voltage (VCCINT) | 5 V nominal (4.75 V to 5.25 V) | — |
| I/O Voltage Support | 3.3 V or 5 V configurable | — |
| Gehäuse | 100-pin Plastic Quad Flat Pack (PQFP, EQFP, EQC100) | TQFP-100 (100-pin Thin Quad Flat Pack) |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | 0 °C to +90 °C (commercial) | -40 C to +85 C (Industrial) |
| In-System Programmability | Yes (IEEE 1149.1 JTAG, 4-pin) | — |
| Reprogram Cycles (typical) | 100 | — |
| RoHS-Status | Not RoHS compliant (legacy Altera MAX 7000) | [DATA_NEEDED: RoHS status - not explicitly stated in provided data] |
| Logic Elements per Macrocell | 36 product terms (expandable) | — |
| User I/Os | — | 84 |
| Logic Elements / Blocks | — | 16 Logic Array Blocks (LABs) |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Operating Frequency | — | 100 MHz |
| Internal Supply Voltage | — | 4.75 V to 5.25 V |
| I/O Supply Voltage | — | 5.0 V |
| Programmable Type | — | In-System Programmable (EEPROM) |
| JTAG / Boundary Scan | — | IEEE Std. 1149.1 compliant |
| PCI Compliance | — | PCI Local Bus Specification Rev. 2.2 (for -10 speed grade) |
| MSL-Level | — | [DATA_NEEDED: MSL rating] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |