EPM7160EQC100-20 vs EPM7160STI100-10 Comparison
Detailed side-by-side comparison of EPM7160EQC100-20 by Altera and EPM7160STI100-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7160EQC100-20 - MAX 7000 CPLD, 160 Macrocells, 100-Pin PQFP
EPM7160EQC100-20 β Last Time Buy
Specification Comparison
| Parameter | EPM7160EQC100-20 | EPM7160STI100-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $17.10 | $90.43 |
| Series | MAX 7000 | β |
| Family | MAX 7000 CPLD | MAX 7000S |
| Architecture | CMOS EEPROM-based, non-volatile | β |
| Usable Gates | 3,200 | 3,200 |
| Macrocells | 160 | 160 |
| Logic Array Blocks (LABs) | 10 | β |
| Maximum User I/Os | 84 | β |
| Pin-to-Pin Propagation Delay (tPD) | 20 ns | β |
| Maximum Internal Frequency (fCNT) | 62.5 MHz | β |
| Supply Voltage (VCCINT) | 5 V nominal (4.75 V to 5.25 V) | β |
| I/O Voltage Support | 3.3 V or 5 V configurable | β |
| Package | 100-pin Plastic Quad Flat Pack (PQFP, EQFP, EQC100) | TQFP-100 (100-pin Thin Quad Flat Pack) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0 Β°C to +90 Β°C (commercial) | -40 C to +85 C (Industrial) |
| In-System Programmability | Yes (IEEE 1149.1 JTAG, 4-pin) | β |
| Reprogram Cycles (typical) | 100 | β |
| RoHS Status | Not RoHS compliant (legacy Altera MAX 7000) | [DATA_NEEDED: RoHS status - not explicitly stated in provided data] |
| Logic Elements per Macrocell | 36 product terms (expandable) | β |
| User I/Os | β | 84 |
| Logic Elements / Blocks | β | 16 Logic Array Blocks (LABs) |
| Propagation Delay (tPD) | β | 10 ns |
| Maximum Operating Frequency | β | 100 MHz |
| Internal Supply Voltage | β | 4.75 V to 5.25 V |
| I/O Supply Voltage | β | 5.0 V |
| Programmable Type | β | In-System Programmable (EEPROM) |
| JTAG / Boundary Scan | β | IEEE Std. 1149.1 compliant |
| PCI Compliance | β | PCI Local Bus Specification Rev. 2.2 (for -10 speed grade) |
| MSL Level | β | [DATA_NEEDED: MSL rating] |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |