EPM7256AEQC208-5N vs EPM7256AETC144-5N Vergleich
Detaillierter Direktvergleich von EPM7256AEQC208-5N von Altera und EPM7256AETC144-5N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM7256AETC144-5N - 256-Macrocell MAX 7000A CPLD | Altera | TQFP-144
EPM7256AETC144-5N ✓ AktivSpezifikationsvergleich
| Parameter | EPM7256AEQC208-5N | EPM7256AETC144-5N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $11,50 | $9,95 |
| Family | MAX 7000A | MAX 7000A |
| Logic Family / Base Technology | CMOS, EEPROM-based | — |
| Usable Gates | 5,000 | 5,000 |
| Macrocells | 256 | — |
| User I/Os | 164 | — |
| Dedicated Inputs | 16 | — |
| Anzahl der Pins | 208 | — |
| Gehäuse | 208-pin PQFP (Plastic Quad Flat Pack) | TQFP-144 (Plastic Thin Quad Flat Pack) |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| Maximum Internal Frequency | 172.4 MHz | 227.3 MHz |
| Pin-to-Pin Propagation Delay (tPD) | 5.5 ns | 4.5 ns |
| Speed Grade | -5 | -5 |
| Betriebstemperatur | 0 C to +70 C (Commercial) | [DATA_NEEDED: operating temperature grade] |
| Programming Interface | JTAG (IEEE Std. 1149.1) / ISP | — |
| Montageart | Surface Mount | — |
| RoHS-Status | unknown | — |
| MSL-Level | [DATA_NEEDED: MSL Level] | — |
| Logic Family | — | CMOS |
| Macro Cells | — | 256 |
| Logic Blocks | — | 16 |
| User I/Os (Mouser listing) | — | 36 |
| User I/Os (DigChip listing) | — | 84 |
| Counter Speed | — | 172.4 MHz |
| Program Memory Type | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes (JTAG) |
| Lead-Free / RoHS | — | Yes (N suffix) |