EPM7256AEQC208-5N vs EPM7256AETC144-5N 对比
详细并排对比 EPM7256AEQC208-5N 出自 Altera 和 EPM7256AETC144-5N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM7256AEQC208-5N | EPM7256AETC144-5N |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $11.50 | $9.95 |
| Family | MAX 7000A | MAX 7000A |
| Logic Family / Base Technology | CMOS, EEPROM-based | — |
| Usable Gates | 5,000 | 5,000 |
| Macrocells | 256 | — |
| User I/Os | 164 | — |
| Dedicated Inputs | 16 | — |
| 引脚数 | 208 | — |
| 封装 | 208-pin PQFP (Plastic Quad Flat Pack) | TQFP-144 (Plastic Thin Quad Flat Pack) |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| Maximum Internal Frequency | 172.4 MHz | 227.3 MHz |
| Pin-to-Pin Propagation Delay (tPD) | 5.5 ns | 4.5 ns |
| Speed Grade | -5 | -5 |
| 工作温度 | 0 C to +70 C (Commercial) | [DATA_NEEDED: operating temperature grade] |
| Programming Interface | JTAG (IEEE Std. 1149.1) / ISP | — |
| 安装类型 | Surface Mount | — |
| RoHS 状态 | unknown | — |
| MSL 等级 | [DATA_NEEDED: MSL Level] | — |
| Logic Family | — | CMOS |
| Macro Cells | — | 256 |
| Logic Blocks | — | 16 |
| User I/Os (Mouser listing) | — | 36 |
| User I/Os (DigChip listing) | — | 84 |
| Counter Speed | — | 172.4 MHz |
| Program Memory Type | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes (JTAG) |
| Lead-Free / RoHS | — | Yes (N suffix) |