EPM7256AETC100-5N vs EPM7256AETC100-10N Vergleich
Detaillierter Direktvergleich von EPM7256AETC100-5N von Altera und EPM7256AETC100-10N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM7256AETC100-5N - 256-Macro MAX 7000A CPLD, 5ns TQFP-100
EPM7256AETC100-5N ⚠ Letzte BestellmöglichkeitAltera
EPM7256AETC100-10N - 256-Macro MAX 7000A CPLD, 10ns, TQFP-100 | Intel (Altera)
EPM7256AETC100-10N ObsoleteSpezifikationsvergleich
| Parameter | EPM7256AETC100-5N | EPM7256AETC100-10N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,75 | $13,10 |
| Family | MAX 7000A | MAX 7000A |
| Series | MAX 7000AE | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 256 | 256 |
| Usable Gates | 5000 (range 600 to 10000) | 5,000 |
| User I/Os | 84 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Pin-to-Pin Delay (tPD) | 5.0 ns | — |
| Counter Frequency (fCNT) | up to 227.3 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| MultiVolt I/O Support | 2.5 V / 3.3 V / 5.0 V | 2.5 V / 3.3 V / 5.0 V |
| Gehäuse | TQFP-100 (1.0 mm pitch, 14x14 mm) | 100-pin TQFP |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | 0C to +70C (Commercial) | — |
| Program Memory | Internal EEPROM | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| RoHS-Status | Compliant (lead-free) | [DATA_NEEDED: not confirmed in provided data] |
| MSL-Level | 3 (168 hours) | — |
| Process Technology | CMOS, EEPROM-based | 0.30 µm EEPROM |
| Security Bit | Programmable | — |
| Maximum User I/Os | — | 84 |
| Logic Elements / LABs | — | 16 Logic Array Blocks |
| Pin-to-Pin Logic Delay | — | 10 ns |
| Maximum Operating Frequency | — | 125 MHz |
| Supply Voltage (Core) | — | 3.3 V |
| Programmability | — | EEPROM, in-system via JTAG (IEEE 1149.1) |
| Betriebstemperaturbereich | — | 0C to +70C (commercial) [DATA_NEEDED: explicit grade from datasheet] |
| Dedicated Inputs | — | 4 (global clock / clear / OE) |
| Lead-Free / Pb-Free | — | [DATA_NEEDED: not confirmed in provided data] |