EPM7256AETC100-5N vs EPM7256AETC100-10N 对比

详细并排对比 EPM7256AETC100-5N 出自 Altera 和 EPM7256AETC100-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM7256AETC100-5N EPM7256AETC100-5N - 256-Macro MAX 7000A CPLD, 5ns TQFP-100

EPM7256AETC100-5N - 256-Macro MAX 7000A CPLD, 5ns TQFP-100

EPM7256AETC100-5N ⚠ 最后一次采购

规格对比

参数 EPM7256AETC100-5N EPM7256AETC100-10N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 Obsolete
库存状态 有库存 有库存
单价(USD) $9.75 $13.10
Family MAX 7000A MAX 7000A
Series MAX 7000AE —
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macro Cells 256 256
Usable Gates 5000 (range 600 to 10000) 5,000
User I/Os 84 —
Logic Array Blocks (LABs) 16 —
Pin-to-Pin Delay (tPD) 5.0 ns —
Counter Frequency (fCNT) up to 227.3 MHz —
Supply Voltage (VCCINT) 3.3 V —
MultiVolt I/O Support 2.5 V / 3.3 V / 5.0 V 2.5 V / 3.3 V / 5.0 V
封装 TQFP-100 (1.0 mm pitch, 14x14 mm) 100-pin TQFP
安装类型 Surface Mount Surface Mount
工作温度 0C to +70C (Commercial) —
Program Memory Internal EEPROM —
In-System Programmability Yes (IEEE 1149.1 JTAG) —
RoHS 状态 Compliant (lead-free) [DATA_NEEDED: not confirmed in provided data]
MSL 等级 3 (168 hours) —
Process Technology CMOS, EEPROM-based 0.30 µm EEPROM
Security Bit Programmable —
Maximum User I/Os — 84
Logic Elements / LABs — 16 Logic Array Blocks
Pin-to-Pin Logic Delay — 10 ns
Maximum Operating Frequency — 125 MHz
Supply Voltage (Core) — 3.3 V
Programmability — EEPROM, in-system via JTAG (IEEE 1149.1)
工作温度范围 — 0C to +70C (commercial) [DATA_NEEDED: explicit grade from datasheet]
Dedicated Inputs — 4 (global clock / clear / OE)
Lead-Free / Pb-Free — [DATA_NEEDED: not confirmed in provided data]

数据手册与资源

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