EPM7256AETC100-5N vs EPM7256AETI100-7N Vergleich
Detaillierter Direktvergleich von EPM7256AETC100-5N von Altera und EPM7256AETI100-7N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM7256AETC100-5N - 256-Macro MAX 7000A CPLD, 5ns TQFP-100
EPM7256AETC100-5N ⚠ Letzte BestellmöglichkeitIntel
EPM7256AETI100-7N - 256-MacroCell MAX 7000A CPLD, 100TQFP | Intel
EPM7256AETI100-7N ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPM7256AETC100-5N | EPM7256AETI100-7N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,75 | $34,20 |
| Family | MAX 7000A | MAX 7000A |
| Series | MAX 7000AE | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macro Cells | 256 | — |
| Usable Gates | 5000 (range 600 to 10000) | 5,000 |
| User I/Os | 84 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Pin-to-Pin Delay (tPD) | 5.0 ns | — |
| Counter Frequency (fCNT) | up to 227.3 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| MultiVolt I/O Support | 2.5 V / 3.3 V / 5.0 V | — |
| Gehäuse | TQFP-100 (1.0 mm pitch, 14x14 mm) | 100-pin TQFP (TQ100, 14x14 mm, 0.5 mm pitch) |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | 0C to +70C (Commercial) | -40C to +85C (Industrial) |
| Program Memory | Internal EEPROM | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| RoHS-Status | Compliant (lead-free) | Compliant |
| MSL-Level | 3 (168 hours) | 3 (168 hours) |
| Process Technology | CMOS, EEPROM-based | — |
| Security Bit | Programmable | — |
| Macrocells | — | 256 |
| Maximum User I/O | — | 84 |
| Logic Elements / Blocks | — | 16 Logic Array Blocks |
| Maximum Operating Frequency | — | 126.6 MHz |
| Propagation Delay (tPD) | — | 7.5 ns |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V |
| Technology | — | CMOS, EEPROM-based configuration |
| Programmability | — | In-system programmable via JTAG (IEEE 1149.1) |