EPM7256AETC100-5N vs EPM7256AETI100-7N 对比

详细并排对比 EPM7256AETC100-5N 出自 Altera 和 EPM7256AETI100-7N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM7256AETC100-5N EPM7256AETC100-5N - 256-Macro MAX 7000A CPLD, 5ns TQFP-100

EPM7256AETC100-5N - 256-Macro MAX 7000A CPLD, 5ns TQFP-100

EPM7256AETC100-5N ⚠ 最后一次采购
Intel
EPM7256AETI100-7N EPM7256AETI100-7N - 256-MacroCell MAX 7000A CPLD, 100TQFP | Intel

EPM7256AETI100-7N - 256-MacroCell MAX 7000A CPLD, 100TQFP | Intel

EPM7256AETI100-7N ⚠ 最后一次采购

规格对比

参数 EPM7256AETC100-5N EPM7256AETI100-7N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 最后采购期
库存状态 有库存 有库存
单价(USD) $9.75 $34.20
Family MAX 7000A MAX 7000A
Series MAX 7000AE —
Device Type CPLD (Complex Programmable Logic Device) CPLD - Complex Programmable Logic Device
Macro Cells 256 —
Usable Gates 5000 (range 600 to 10000) 5,000
User I/Os 84 —
Logic Array Blocks (LABs) 16 —
Pin-to-Pin Delay (tPD) 5.0 ns —
Counter Frequency (fCNT) up to 227.3 MHz —
Supply Voltage (VCCINT) 3.3 V —
MultiVolt I/O Support 2.5 V / 3.3 V / 5.0 V —
封装 TQFP-100 (1.0 mm pitch, 14x14 mm) 100-pin TQFP (TQ100, 14x14 mm, 0.5 mm pitch)
安装类型 Surface Mount Surface Mount
工作温度 0C to +70C (Commercial) -40C to +85C (Industrial)
Program Memory Internal EEPROM —
In-System Programmability Yes (IEEE 1149.1 JTAG) —
RoHS 状态 Compliant (lead-free) Compliant
MSL 等级 3 (168 hours) 3 (168 hours)
Process Technology CMOS, EEPROM-based —
Security Bit Programmable —
Macrocells — 256
Maximum User I/O — 84
Logic Elements / Blocks — 16 Logic Array Blocks
Maximum Operating Frequency — 126.6 MHz
Propagation Delay (tPD) — 7.5 ns
Core Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 3.3 V
Technology — CMOS, EEPROM-based configuration
Programmability — In-system programmable via JTAG (IEEE 1149.1)

数据手册与资源

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