EPM7256AETC100-7N vs EPM7256AETC100-5N Vergleich
Detaillierter Direktvergleich von EPM7256AETC100-7N von Intel und EPM7256AETC100-5N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPM7256AETC100-7N - 256-Macrocell MAX 7000A CPLD, 3.3V, 100TQFP | Intel
EPM7256AETC100-7N NrndAltera
EPM7256AETC100-5N - 256-Macro MAX 7000A CPLD, 5ns TQFP-100
EPM7256AETC100-5N ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPM7256AETC100-7N | EPM7256AETC100-5N |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $48,75 | $9,75 |
| Series | MAX 7000A | MAX 7000AE |
| Programmable Type | In System Programmable (ISP) | — |
| Number of Macrocells | 256 | — |
| Number of Logic Elements/Blocks | 16 | — |
| Number of User I/Os | 84 | — |
| Number of Gates | 5000 | — |
| Propagation Delay tPD (max) | 7.5 ns | — |
| Maximum Frequency fCNT | 126.6 MHz | — |
| Supply Voltage - Internal | 3.0 V to 3.6 V | — |
| Betriebstemperatur | 0 C to 70 C (Commercial) | 0C to +70C (Commercial) |
| Montageart | Surface Mount | Surface Mount |
| Gehäuse | 100-pin TQFP (14 x 14 mm) | TQFP-100 (1.0 mm pitch, 14x14 mm) |
| Technology | CMOS, EEPROM-based | — |
| Programming Interface | IEEE 1149.1 (JTAG) | — |
| RoHS-Status | Compliant | Compliant (lead-free) |
| Family | — | MAX 7000A |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 256 |
| Usable Gates | — | 5000 (range 600 to 10000) |
| User I/Os | — | 84 |
| Logic Array Blocks (LABs) | — | 16 |
| Pin-to-Pin Delay (tPD) | — | 5.0 ns |
| Counter Frequency (fCNT) | — | up to 227.3 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| MultiVolt I/O Support | — | 2.5 V / 3.3 V / 5.0 V |
| Program Memory | — | Internal EEPROM |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| MSL-Level | — | 3 (168 hours) |
| Process Technology | — | CMOS, EEPROM-based |
| Security Bit | — | Programmable |