EPM7256ATI144-10 vs EPM7256AQC208-7 Vergleich
Detaillierter Direktvergleich von EPM7256ATI144-10 von Altera und EPM7256AQC208-7 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM7256ATI144-10 | EPM7256AQC208-7 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $10,95 | $27,20 |
| Family | MAX 7000A | MAX 7000A |
| Macrocells | 256 | 256 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum Usable Gates | 5,000 | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Frequency (fCNT) | 93.5 MHz | — |
| User I/O Pins | 100 | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Voltage (VCCIO) | 2.5 V or 3.3 V | — |
| Program Memory Type | EEPROM (non-volatile) | — |
| In-System Programming | Yes (IEEE 1149.1 JTAG) | — |
| Gehäuse | 144-pin TQFP | 208-Pin PQFP (28 x 28 mm) |
| Betriebstemperaturbereich | -40C to +85C (Industrial) | 0C to +70C (commercial) |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | Non-compliant (legacy Altera marking) | [DATA_NEEDED: RoHS status] |
| Process Technology | EEPROM-based CMOS | — |
| Programmable Type | — | In System Programmable (ISP), EEPROM-based |
| Usable Gates | — | 5,000 |
| Maximum User I/O Pins | — | 164 |
| Pin-to-Pin Logic Delay (tPD) | — | 7 ns |
| Maximum Counter Frequency | — | 125 MHz |
| Internal Toggle Frequency | — | 227.3 MHz |
| Supply Voltage - Internal | — | 3.0 V to 3.6 V |
| I/O Voltage Compatibility | — | 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O) |
| Supplier Device Package | — | 208-PQFP (28x28) |
| JTAG Interface | — | IEEE 1149.1 (JTAG) boundary scan |
| Configuration Memory | — | EEPROM (non-volatile) |
| Speed Grade | — | -7 |
| MSL-Level | — | [DATA_NEEDED: MSL level] |