EPM7256EGI192-15 vs EPM7256EGC192-12 Vergleich
Detaillierter Direktvergleich von EPM7256EGI192-15 von Altera und EPM7256EGC192-12 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM7256EGI192-15 | EPM7256EGC192-12 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $52,00 | $17,85 |
| Family | MAX 7000 | MAX 7000 |
| Series | MAX 7000E | — |
| Macro Cells | 256 | — |
| Usable Gates | 5,000 | 5,000 |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum Operating Frequency | 76.9 MHz | 90.9 MHz |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Supply Voltage (VCCINT) | 5 V | 4.75 V to 5.25 V (5 V nominal) |
| User I/O Pins | 192 | 164 |
| Dedicated Input Pins | 12 | — |
| Programmable Power Mode | Yes (per-macrocell) | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| Gehäuse | 192-pin CPGA (Ceramic Pin Grid Array) | 192-pin CPGA (Ceramic Pin Grid Array) |
| Operating Temperature Grade | Industrial (-40C to +85C) | — |
| RoHS-Status | Non-compliant (ceramic CPGA, contains lead) | Compliant |
| Montageart | Through-Hole (Socket) | Through Hole (PGA socket) |
| Device Logic Cells | — | 256 macrocells |
| Propagation Delay (tPD) | — | 12 ns |
| Technology | — | CMOS, EEPROM-based |
| Betriebstemperatur | — | 0C to +70C (commercial) |
| Programmable Interface | — | JTAG (IEEE 1149.1) / ISP |
| Logic Blocks (LABs) | — | 16 |
| Macrocells per LAB | — | 16 |
| Lead-Free | — | Yes |
| JEDEC Package Code | — | S-CPGA-P192 |