EPM7256SQC208-15 vs EPM7256SQC208-7 Vergleich
Detaillierter Direktvergleich von EPM7256SQC208-15 von Altera und EPM7256SQC208-7 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM7256SQC208-15 | EPM7256SQC208-7 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $3,65 | $0,00 |
| Family | MAX 7000S | — |
| Series | EPM7256 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 256 | 256 |
| Logic Array Blocks (LABs) | 16 | — |
| Usable Gates | 5000 | 5,000 |
| User I/O Pins | 164 | 164 |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V | — |
| Betriebstemperaturbereich | 0 C to +70 C (Commercial) | Commercial (0C to +70C) |
| Gehäuse | 208-pin PQFP (28x28 mm) | 208-pin PQFP (28 x 28 mm, 0.5 mm pitch) |
| Montageart | Surface Mount | Surface Mount |
| Programmable Power Mode | Yes (per-macrocell turbo-bit) | — |
| JTAG (IEEE 1149.1) Boundary-Scan | Yes | — |
| In-System Programmability (ISP) | Yes | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| RoHS-Status | Contains lead / RoHS non-compliant (per third-party listing) | [DATA_NEEDED: RoHS status] |
| Lead-Free Status | Contains lead | — |
| Device Family | — | MAX 7000S (EPM7256S) |
| Propagation Delay (tPD) | — | 7.5 ns |
| Maximum Operating Frequency (fMAX) | — | 128.2 MHz |
| Supply Voltage (VCC) | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Minimum DC Input Voltage | — | -0.5 V |
| Input Undershoot Tolerance | — | -2.0 V for <100 mA, <20 ns |
| Speed Grade | — | -7 (7.5 ns) |
| MSL-Level | — | [DATA_NEEDED: MSL level] |
| Logic Levels | — | 5.0 V CMOS/TTL compatible |