EPM7256SQC208-7N vs EPM7256SRC208-10 Vergleich

Detaillierter Direktvergleich von EPM7256SQC208-7N von Altera und EPM7256SRC208-10 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM7256SQC208-7N EPM7256SRC208-10
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $27,20 $27,20
Family MAX 7000S MAX 7000S
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 256 —
Usable Gates 5,000 —
Logic Array Blocks (LABs) 16 —
User I/O Pins 164 —
Speed Grade -7 (7.5 ns pin-to-pin) —
Maximum Frequency 128.2 MHz —
Supply Voltage (VCC) 5 V —
Technology CMOS EEPROM —
Configuration Memory Non-volatile EEPROM (no external config needed) —
Gehäuse 208-pin PQFP (Plastic Quad Flat Pack) 208-pin RQFP (BFQFP) exposed pad, 28x28 mm
Montageart Surface Mount Surface Mount
Betriebstemperatur Commercial (0C to +70C) 0C to +70C (TA, commercial)
JTAG Interface IEEE 1149.1 boundary-scan (ISP capable) —
Minimum DC Input Voltage -0.5 V —
Input Undershoot Tolerance -2.0 V for <100 mA, <20 ns —
RoHS-Status Compliant (N suffix = lead-free) [DATA_NEEDED: RoHS status]
Pin-to-Pin Delay (tPD) 7.5 ns —
Open-Drain Output Optional per I/O pin —
Number of Macrocells — 256
Number of Logic Array Blocks (LABs) — 16
Number of Gates — 5000
Number of User I/O Pins — 164
Maximum Propagation Delay (tPD) — 10 ns
Maximum Operating Frequency — 100 MHz
Supply Voltage (Internal) — 4.75 V to 5.25 V
Programmable Type — In System Programmable (ISP, JTAG)
Configuration Technology — EEPROM
Terminal Form — Gull Wing
Package Shape — Square
Product Status — Obsolete

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