EPM7256SQC208-7N vs EPM7256SRC208-10 对比
详细并排对比 EPM7256SQC208-7N 出自 Altera 和 EPM7256SRC208-10 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM7256SQC208-7N | EPM7256SRC208-10 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $27.20 | $27.20 |
| Family | MAX 7000S | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 256 | — |
| Usable Gates | 5,000 | — |
| Logic Array Blocks (LABs) | 16 | — |
| User I/O Pins | 164 | — |
| Speed Grade | -7 (7.5 ns pin-to-pin) | — |
| Maximum Frequency | 128.2 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Technology | CMOS EEPROM | — |
| Configuration Memory | Non-volatile EEPROM (no external config needed) | — |
| 封装 | 208-pin PQFP (Plastic Quad Flat Pack) | 208-pin RQFP (BFQFP) exposed pad, 28x28 mm |
| 安装类型 | Surface Mount | Surface Mount |
| 工作温度 | Commercial (0C to +70C) | 0C to +70C (TA, commercial) |
| JTAG Interface | IEEE 1149.1 boundary-scan (ISP capable) | — |
| Minimum DC Input Voltage | -0.5 V | — |
| Input Undershoot Tolerance | -2.0 V for <100 mA, <20 ns | — |
| RoHS 状态 | Compliant (N suffix = lead-free) | [DATA_NEEDED: RoHS status] |
| Pin-to-Pin Delay (tPD) | 7.5 ns | — |
| Open-Drain Output | Optional per I/O pin | — |
| Number of Macrocells | — | 256 |
| Number of Logic Array Blocks (LABs) | — | 16 |
| Number of Gates | — | 5000 |
| Number of User I/O Pins | — | 164 |
| Maximum Propagation Delay (tPD) | — | 10 ns |
| Maximum Operating Frequency | — | 100 MHz |
| Supply Voltage (Internal) | — | 4.75 V to 5.25 V |
| Programmable Type | — | In System Programmable (ISP, JTAG) |
| Configuration Technology | — | EEPROM |
| Terminal Form | — | Gull Wing |
| Package Shape | — | Square |
| Product Status | — | Obsolete |