EPM7256SQC208-7N vs EPM7256SRC208-15N Vergleich
Detaillierter Direktvergleich von EPM7256SQC208-7N von Altera und EPM7256SRC208-15N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM7256SQC208-7N | EPM7256SRC208-15N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $27,20 | $27,20 |
| Family | MAX 7000S | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 256 | 256 |
| Usable Gates | 5,000 | 5,000 |
| Logic Array Blocks (LABs) | 16 | 16 |
| User I/O Pins | 164 | 164 |
| Speed Grade | -7 (7.5 ns pin-to-pin) | — |
| Maximum Frequency | 128.2 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Technology | CMOS EEPROM | — |
| Configuration Memory | Non-volatile EEPROM (no external config needed) | EEPROM (non-volatile) |
| Gehäuse | 208-pin PQFP (Plastic Quad Flat Pack) | 208-pin RQFP (PowerQuad Flat Pack) |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | Commercial (0C to +70C) | 0C to +70C (commercial) |
| JTAG Interface | IEEE 1149.1 boundary-scan (ISP capable) | — |
| Minimum DC Input Voltage | -0.5 V | — |
| Input Undershoot Tolerance | -2.0 V for <100 mA, <20 ns | — |
| RoHS-Status | Compliant (N suffix = lead-free) | Compliant (N suffix) |
| Pin-to-Pin Delay (tPD) | 7.5 ns | 15 ns |
| Open-Drain Output | Optional per I/O pin | — |
| Series | — | MAX 7000S |
| Maximum Counter Frequency | — | 76.9 MHz |
| Versorgungsspannung | — | 5 V |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| I/O Standard | — | 5 V TTL/CMOS compatible |
| Lead Free | — | Yes (N suffix) |
| MSL-Level | — | [DATA_NEEDED: MSL level] |
| Number of Terminals | — | 208 |