EPM7256SQI208-10 vs EPM7256SQC208-15 Vergleich
Detaillierter Direktvergleich von EPM7256SQI208-10 von Altera und EPM7256SQC208-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM7256SQI208-10 | EPM7256SQC208-15 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,40 | $3,65 |
| Device Family | MAX 7000 (EPM7256) | — |
| Macrocells | 256 | 256 |
| Usable Gates | 5000 | 5000 |
| Logic Array Blocks | 16 | — |
| Maximum User I/O Pins | 164 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Supply Voltage Range | 4.5 V to 5.5 V | — |
| Technology | CMOS EEPROM | — |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| In-System Programmable | Yes (IEEE 1149.1 JTAG) | — |
| Gehäuse | 208-pin PQFP (QFP208) | 208-pin PQFP (28x28 mm) |
| Package Body Material | Plastic/Epoxy | — |
| Terminal Form | Gull Wing | — |
| Betriebstemperaturbereich | -40 C to +85 C (Industrial) | 0 C to +70 C (Commercial) |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | [DATA_NEEDED: RoHS status] | Contains lead / RoHS non-compliant (per third-party listing) |
| JESD-30 Package Code | S-PQFP-G208 | — |
| JESD-609 Terminal Finish Code | E3 | — |
| Family | — | MAX 7000S |
| Series | — | EPM7256 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 16 |
| User I/O Pins | — | 164 |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Supply Voltage (VCCINT) | — | 4.75 V to 5.25 V |
| Programmable Power Mode | — | Yes (per-macrocell turbo-bit) |
| JTAG (IEEE 1149.1) Boundary-Scan | — | Yes |
| In-System Programmability (ISP) | — | Yes |
| Lead-Free Status | — | Contains lead |